DE Syllabus
| Topic | Subtopics / What to Cover |
|---|---|
| Number Systems | Decimal, Binary, Octal, Hexadecimal ⭐ Base conversion ⭐ |
| Binary Arithmetic | Addition, Subtraction ⭐ 1’s & 2’s complement ⭐ |
| Codes | BCD, Excess-3 Gray code ⭐ Error detection codes |
| Boolean Algebra | Laws, Theorems ⭐ Simplification ⭐ |
| Logic Gates | AND, OR, NOT ⭐ NAND, NOR, XOR, XNOR ⭐ |
| Universal Gates | NAND-only ⭐ NOR-only implementation ⭐ |
| Boolean Functions | Canonical forms ⭐ Minterms & Maxterms ⭐ |
| K-Map | 2, 3, 4 variable K-Map ⭐ Don’t care conditions ⭐ |
| Combinational Circuits | Half/Full Adder ⭐ Subtractor ⭐ |
| Multiplexers | 2:1, 4:1, 8:1 ⭐ Implementation of logic ⭐ |
| Demultiplexers | Function & applications |
| Encoders | Priority encoder ⭐ |
| Decoders | 2:4, 3:8 decoder ⭐ |
| Arithmetic Circuits | Parallel adder ⭐ Carry look-ahead ⭐ |
| Comparators | Magnitude comparator |
| Sequential Circuits | Concept of memory ⭐ |
| Flip-Flops | SR, JK, D, T ⭐ Truth tables ⭐ |
| FF Conversions | SR↔JK↔D↔T ⭐ |
| Counters | Asynchronous ⭐ Synchronous ⭐ |
| Counter Types | Up, Down, Mod-N ⭐ |
| Shift Registers | SISO, SIPO ⭐ PISO, PIPO ⭐ |
| Registers | Universal shift register |
| Timing Analysis | Setup time ⭐ Hold time ⭐ |
| Finite State Machines | Moore ⭐ Mealy ⭐ |
| FSM Design | State diagram ⭐ State table ⭐ |
| Memory | ROM, RAM ⭐ SRAM vs DRAM ⭐ |
| PLA / PAL | Architecture ⭐ Applications |
| ADC & DAC | Types ⭐ Resolution ⭐ |