Memory Chip Organization and Interleaving

COA
└── Memory Organization
    ├── Memory Hierarchy
    ├── Semiconductor Memory
    ├── Memory Chip Organization 👈
    │   ├── Address lines
    │   ├── Data lines
    │   ├── Capacity
    │   ├── Memory chips
    │   ├── Memory expansion
    │   └── Memory interfacing
    ├── Memory Interleaving 👈
    └── Cache Memory

1. Understanding Chip Specifications

• Format: ⭐$CapacityOfChip = (\text{Number of Words}) × (\text{Word Size in bits})$
  • Example: 64K × 1 = 64K words, each word is 1 bit wide → 64K bits total.
  • Example: 512K × 8 = 512K words, each word is 8 bits wide (1 byte) → 512K×8512K times 8 bits total.

2. Converting to Bytes and Bits

• Bits to Bytes: Divide by 8.
• Bytes to Bits: Multiply by 8.

3. Calculating Number of Chips Needed
Formula:

$Number of chips= \frac{\text{Required capacity in bits}}{\text{Capacity per chip in bits}}$

Example:

• Required: 512K × 8 bits = 4096K bits.
• Per chip: 64K × 1 bit = 64K bits.
• Chips needed= 4096K / 64K = 64

4. Organization for Required Word Width

• To get 8-bit word width from 1-bit chips, group 8 chips in parallel (same address lines, separate data lines).
• To get the total memory size, stack enough such groups.

Example for 512K × 8 using 64K × 1 chips:

• First, 8 chips in parallel → 64K × 8.
• Required 512K × 8 → 512K / 64K = 8 such groups.
• Total chips = 8 chips/group×8 groups = 64 chips